Design and Implementation of QPSK Modulator Using FPGA Based on DDSalgorithm
DOI:
https://doi.org/10.31663/utjes.15.1.678Keywords:
DDS, Digital Modulators, Look Up Table, LUT, VHDLAbstract
Digital modulators have become a hot research topic because of the progress in Radio Frequency (RF) frontend terminals and systems on chip industry. But with all the progress that has been made, the implementationcost is still a challenge. This research paper presents a new architecture of construction Quadrature PhaseShift Keying (QPSK) modulator in VHDL at the lowest possible implementation cost. Four different carriersignals were generated using two 8-bit accumulators and 64 values Look Up Table (LUT) depending on theconcept of Direct Digital Synthesizer (DDS) technique. The first accumulator operates on the rising edge ofthe clock, while the second one operates on the falling edge of the clock. The most significant bit in eachaccumulator was reversed using the XOR logic function. This process represents generating out-of-phasesignals (180-degree phase difference compared with the original ones). The whole implementation processwas done directly in Very high speed integrated circuit Hardware Descriptive Language (VHDL) using XILINXVivado without the assistance of any co- simulation tool like DSP Builder Tools or Xilinx System Generator.The presented fulfillment technique based on the 64 values LUT has reduced the utilization resources bymore than 70%.
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